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tda8768a 12-bit, 70 msps analog-to-digital converter (adc) rev. 02 03 july 2002 product data 1. description the tda8768ah is a bicmos 12-bit analog-to-digital converter (adc) optimized for gsm and edge cellular infrastructures, professional telecommunications and imaging, and advanced fm radio. it converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 mhz. all static digital inputs (sh, ce and otc) are ttl and cmos compatible and all outputs are cmos compatible. a sine wave clock input signal can also be used. 2. features n 12-bit resolution n sampling rate up to 70 mhz n - 3 db bandwidth of 245 mhz n 5 v power supplies and 3.3 v output power supply n binary or twos complement cmos outputs n in-range cmos compatible output n ttl and cmos compatible static digital inputs n ttl and cmos compatible digital outputs n differential ac or pecl clock input; ttl compatible n power dissipation 550 mw (typical) n low analog input capacitance (typical 2 pf), no buffer ampli?er required n integrated sample-and-hold ampli?er n differential analog input n external amplitude range control n voltage controlled regulator included n - 40 c to +85 c ambient temperature. 3. applications n high-speed analog-to-digital conversion for: u cellular infrastructure (gsm and edge) u professional telecommunication u advanced fm radio u radar u imaging (camera scanner) u set top box (stb) u medical imaging.
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 2 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 4. quick reference data 5. ordering information table 1: quick reference data symbol parameter conditions min typ max unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 3.6 v i cca analog supply current - 78 87 ma i ccd digital supply current - 27 30 ma i cco output supply current f clk =20mhz f i = 400 khz - 34ma inl integral non-linearity f clk =20mhz f i = 400 khz - 2.6 4.5 lsb dnl differential non-linearity (no missing code) f clk =20mhz f i = 400 khz - 0.5 +1.1 - 0.95 lsb f clk(max) maximum clock frequency ---- tda8768ah/4 40 - - mhz tda8768ah/5 55 - mhz tda8768ah/7 70 - - mhz p tot total power dissipation f clk =55mhz f i =20mhz - 550 660 mw table 2: ordering information type number package sampling frequency (mhz) name description version tda8768ah/4 qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 40 tda8768ah/5 55 tda8768ah/7 70
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 3 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 6. block diagram fig 1. block diagram. 005aaa024 d11 msb data outputs 19 21 d10 22 d9 23 d8 24 d7 25 d6 26 d5 27 d4 d3 28 29 43 42 39 11 6 to 10, 13, 14, 16 v ref sh n.c. d2 30 d1 31 d0 lsb 32 v cco 33 ir 34 20 18 cmos outputs latches analog-to-digital converter clock driver 15 v ccd2 37 v ccd1 41 v cca4 3 v cca3 2 v cca1 36 clk 35 clk cmos output ognd overflow/ underflow latch ce otc amp sample- and-hold tda8768a 17 dgnd2 38 dgnd1 40 agnd4 4 agnd3 44 agnd1 v i v i 12 vref reference fs ref cmadc reference 1 cmadc 5 dec
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 4 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration. tda8768ah fce002 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 cmadc dec n.c. n.c. n.c. n.c. n.c. v cca1 v cca3 v ref agnd3 fs ref n.c. n.c. n.c. ir d11 d10 dgnd2 v ccd2 ce otc d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd dgnd1 agnd4 agnd1 v ccd1 v cca4 clk v cco clk sh v i v i table 3: pin description symbol pin description cmadc 1 regulator output common mode adc input v cca1 2 analog supply voltage 1 (+5 v) v cca3 3 analog supply voltage 3 (+5 v) agnd3 4 analog ground 3 dec 5 decoupling node n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected vref 11 reference voltage input fsref 12 full-scale reference output
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 5 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8. limiting values n.c. 13 not connected n.c. 14 not connected v ccd2 15 digital supply voltage 2 (+5 v) n.c. 16 not connected dgnd2 17 digital ground 2 otc 18 control input twos complement output; active high ce 19 chip enable input (cmos level; active low) ir 20 in-range output d11 21 data output; bit 11 (msb) d10 22 data output; bit 10 d9 23 data output; bit 9 d8 24 data output; bit 8 d7 25 data output; bit 7 d6 26 data output; bit 6 d5 27 data output; bit 5 d4 28 data output; bit 4 d3 29 data output; bit 3 d2 30 data output; bit 2 d1 31 data output; bit 1 d0 32 data output; bit 0 (lsb) v cco 33 output supply voltage (+3.3 v) ognd 34 output ground clk 35 complementary clock input clk 36 clock input v ccd1 37 digital supply voltage 1 (+5 v) dgnd1 38 digital ground 1 sh 39 sample-and-hold enable input (cmos level; active high) agnd4 40 analog ground 4 v cca4 41 analog supply voltage 4 (+5 v) v i 42 analog input voltage v i 43 complementary analog input voltage agnd1 44 analog ground 1 table 3: pin description continued symbol pin description table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] - 0.3 +7.0 v v ccd digital supply voltage [1] - 0.3 +7.0 v v cco output supply voltage [1] - 0.3 +7.0 v
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 6 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. [1] the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v cc are respected. 9. thermal characteristics 10. characteristics d v cc supply voltage difference v cca - v ccd - 1.0 +1.0 v v ccd - v cco - 1.0 +4.0 v v cca - v cco - 1.0 +4.0 v v i , v i input voltage at pins 42 and 43 referenced to agnd 0.3 v cca v v clk(p-p) input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) -v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c t j junction temperature - 150 c table 4: limiting values continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 5: thermal characteristics symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 75 k/w table 6: characteristics v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 3.6 v i cca analog supply current i - 78 87 ma i ccd digital supply current i - 27 30 ma i cco output supply current f clk = 20 mhz; f i = 400 khz i - 3 4 ma f clk = 40 mhz; f i = 4.43 mhz c - 6.2 9 ma f clk = 55 mhz; f i = 20 mhz i - 9.5 12 ma inputs
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 7 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. clk and clk (referenced to dgnd) [2] v il low-level input voltage pecl mode; v ccd = 5 v i 3.19 - 3.52 v ttl mode c 0 - 0.8 v v ih high-level input voltage pecl mode; v ccd = 5 v i 3.83 - 4.12 v ttl mode c 2.0 - v ccd v i il low-level input current v clk or v clk = 3.19 v c - 10 - - m a i ih high-level input current v clk or v clk = 3.83 v c - - 10 m a d v clk(p-p) differential ac input voltage for switching (v clk(p-p) - v clk(p-p) ) ac driving mode; dc voltage level = 2.5 v c 1 1.5 2.0 v r i input resistance f clk = 55 mhz d 2 - - k w c i input capacitance f clk = 55 mhz d - - 2 pf otc, sh and ce (referenced to dgnd); see tables 7 and 8 v il low-level input voltage i 0 - 0.8 v v ih high-level input voltage i 2.0 - v ccd v i il low-level input current v il = 0.8 v i - 20 - - m a i ih high-level input current v ih = 2.0 v i - - 20 m a v i and v i (referenced to agnd); see ta b l e 7 , v ref =v cca3 - 1.75 v i il low-level input current sh = high c - 10 - m a i ih high-level input current sh = high c - 10 - m a r i input resistance f i = 20 mhz d - 14 - m w c i input capacitance f i = 20 mhz d - 450 - ff v i(cm) common mode input voltage v i = v i ; output code 2047 c v cca3 - 1.7 v cca3 - 1.6 v cca3 - 1.2 v voltage controlled regulator output cmadc v o(cm) common mode output voltage i - v cca3 - 1.6 - v i l load current i - 1 2 ma voltage input v ref [3] v ref full-scale ?xed voltage f i = 20 mhz; f clk = 55 msps c - v cca3 - 1.75 -v i ref input current at v ref c - 0.3 10 m a v i(p-p) - v i(p-p) input voltage amplitude (peak-to-peak value) v ref =v cca3 - 1.75 v v i(cm) =v cca3 - 1.6 v c - 1.9 - v voltage controlled regulator output fs ref v o(ref) 1.9 v full-scale output voltage i - v cca3 - 1.75 -v outputs (referenced to ognd) digital outputs d11 to d0 and ir (referenced to ognd) v ol low-level output voltage i ol = 2 ma i 0 - 0.5 v table 6: characteristics continued v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 8 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. v oh high-level output voltage i oh = - 0.4 ma i v cco - 0.5 -v cco v i o output current in 3-state output level between 0.5 v and v cco i - 20 - +20 m a switching characteristics clock frequency f clk ; see figure 3 f clk(min) minimum clock frequency sh = high c - - 7 mhz f clk(max) maximum clock frequency tda8768ah/4 c 40 - - mhz tda8768ah/5 i 55 - - mhz tda8768ah/7 c 70 - - mhz t clkh clock pulse width high f i = 20 mhz c 6.8 - - ns t clkl clock pulse width low f i = 20 mhz c 6.8 - - ns analog signal processing; 50% clock duty factor; v i - v i = 1.9 v; v ref =v cca3 - 1.75 v; see table 7 linearity inl integral non-linearity f clk = 20 mhz; f i = 400 khz i - 2.6 4.5 lsb dnl differential non-linearity f clk = 20 mhz; f i = 400 khz (no missing code guaranteed) i- 0.5 +1.1 - 0.95 lsb o err offset error v cca =v ccd =5v; v cco = 3.3 v; t amb =25 c; output code = 2047 c - 25 5 25 mv e g gain error amplitude; spread from device to device v cca =v ccd =5v; v cco = 3.3 v; t amb =25 c c - 7 - +7 %fs bandwidth (f clk = 55 mhz) [4] b analog bandwidth - 3 db; full-scale input c 220 245 - mhz harmonics h 2 second harmonic tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - - 78 - dbfs f i =10mhz c - - 77 - dbfs f i =15mhz c - - 74 - dbfs f i =20mhz c - - 71 - dbfs second harmonic tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - - 77 - dbfs f i =10mhz c - - 77 - dbfs f i =15mhz c - - 76 - dbfs f i =20mhz i - - 73 - dbfs second harmonic tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - - 76 - dbfs f i =10mhz c - - 74 - dbfs f i =15mhz c - - 70 - dbfs table 6: characteristics continued v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 9 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. h 3 third harmonic tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - - 74 - dbfs f i =10mhz c - - 74 - dbfs f i =15mhz c - - 74 - dbfs f i =20mhz c - - 73 - dbfs third harmonic tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - - 74 - dbfs f i =10mhz c - - 74 - dbfs f i =15mhz c - - 74 - dbfs f i =20mhz i - - 72 - dbfs third harmonic tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - - 74 - dbfs f i =10mhz c - - 74 - dbfs f i =15mhz c - - 73 - dbfs total harmonic distortion [5] thd total harmonic distortion tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - - 68 - dbfs f i =10mhz c - - 68 - dbfs f i =15mhz c - - 68 - dbfs f i =20mhz c - - 68 - dbfs total harmonic distortion tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - - 68 - dbfs f i =10mhz c - - 68 - dbfs f i =15mhz c - - 68 - dbfs f i =20mhz i - - 68 - dbfs total harmonic distortion tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - - 68 - dbfs f i =10mhz c - - 67 - dbfs f i =15mhz c - - 67 - dbfs thermal noise (f clk = 55 mhz) n th(rms) thermal noise (rms value) shorted input; sh = high; f clk =55mhz c - 0.45 - lsb signal-to-noise ratio [6] snr signal-to-noise ratio tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - 64 - dbfs f i = 10 mhz c - 64 - dbfs f i = 15 mhz c - 64 - dbfs f i = 20 mhz c - 64 - dbfs signal-to-noise ratio tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - 64 - dbfs f i = 10 mhz c - 64 - dbfs f i = 15 mhz c - 64 - dbfs f i = 20 mhz i - 64 - dbfs signal-to-noise ratio tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - 64 - dbfs f i = 10 mhz c - 64 - dbfs f i = 15 mhz c - 63 - dbfs table 6: characteristics continued v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 10 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. spurious free dynamic range; see figure 7 , 13 and 14 sfdr spurious free dynamic range tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - 72 - dbfs f i = 10 mhz c - 71 - dbfs f i = 15 mhz c - 71 - dbfs f i = 20 mhz c - 69 - dbfs spurious free dynamic range tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - 72 - dbfs f i = 10 mhz c - 71 - dbfs f i = 15 mhz c - 71 - dbfs f i = 20 mhz i - 69 - dbfs spurious free dynamic range tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - 70 - dbfs f i = 10 mhz c - 69 - dbfs f i = 15 mhz c - 69 - dbfs effective number of bits [7] enob effective number of bits tda8768ah/4 (f clk = 40 mhz) f i = 4.43 mhz c - 10.1 - bits f i = 10 mhz c - 10.1 - bits f i = 15 mhz c - 10.1 - bits f i = 20 mhz c - 10 - bits effective number of bits tda8768ah/5 (f clk = 55 mhz) f i = 4.43 mhz c - 10.1 - bits f i = 10 mhz c - 10.1 - bits f i = 15 mhz c - 10 - bits f i = 20 mhz i - 10 - bits effective number of bits tda8768ah/7 (f clk = 70 mhz) f i = 4.43 mhz c - 10 - bits f i = 10 mhz c - 10 - bits f i = 15 mhz c - 10 - bits intermodulation; (f clk = 55 mhz; f i = 20 mhz) [8] ttir two-tone intermodulation rejection c- - 68 - db d 3 third-order intermodulation distortion c- - 70 - db bit error rate (f clk = 55 mhz) ber bit error rate f i = 20 mhz; v i = 16 lsb at code 2047 c-10 - 14 - times/ sample timing (c l =10pf) [9] t d(s) sampling delay time c - 0.25 1 ns t h(o) output hold time c 4 6.4 - ns t d(o) output delay time c - 9.0 13 ns table 6: characteristics continued v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 11 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. [1] d = guaranteed by design; c = guaranteed by characterization; i = 100% industrially tested. [2] the circuit has two clock inputs: clk and clk. there are 5 modes of operation: a) pecl mode 1: (dc level vary 1:1 with v ccd ) clk and clk inputs are at differential pecl levels. b) pecl mode 2: (dc level vary 1:1 with v ccd ) clk input is at pecl level and sampling is taken on the falling edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. c) pecl mode 3: (dc level vary 1:1 with v ccd ) clk input is at pecl level and sampling is taken on the rising edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. d) differential ac driving mode 4: when driving the clk input directly and with any ac signal of minimum 1 v (p-p) and with a dc level of 2.5 v, the sampling takes place at the falling edge of the clock signal. when driving the clk input with the same signal, sampling takes place at the rising edge of the clock signal. it is recommended to decouple the clk or clk input to dgnd via a 100 nf capacitor. e) ttl mode 1: clk input is at ttl level and sampling is taken on the falling edge of the clock input signal. in that case clk pin has to be connected to the ground. [3] the adc input range can be adjusted with an external reference connected to v ref pin. this voltage has to be referenced to v cca ; see figure 12 . [4] the - 3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input being a full-scale sine wave. [5] total harmonic distortion (thd) is obtained with the addition of the ?rst ?ve harmonics: where f is the fundamental harmonic referenced at 0 db for a full-scale sine wave input; see figure 6 . [6] signal-to-noise ratio (snr) takes into account all harmonics above ?ve and noise up to nyquist frequency; see figure 8 . [7] effective number of bits are obtained via a fast fourier transform (fft). the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to sinad is given by sinad = enob 6.02 + 1.76 db; see figure 5 . [8] intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 mhz. the two input signals have t he same amplitude and the total amplitude of both signals provides full-scale to the converter ( - 6 db below full scale for each input signal). d3 (im3) is the ratio of the rms value of either input tone to the rms value of the worst case third order intermodulation product. [9] output data acquisition: the output data is available after the maximum delay of t d ; see figure 3 . 3-state output delay times; see figure 4 t dzh enable high c - 5.1 9.0 ns t dzl enable low c - 7.0 11 ns t dhz disable high c - 9.7 14 ns t dlz disable low c - 9.5 13 ns table 6: characteristics continued v cca =v 2 to v 44 , v 3 to v 4 and v 41 to v 40 = 4.75 to 5.25 v; v ccd =v 37 to v 38 and v 15 to v 17 = 4.75 to 5.25 v; v cco =v 33 to v 34 = 3.0 to 3.6 v; agnd and dgnd shorted together; t amb = - 40 to 85 c; v i(p-p) - v i(p-p) = 1.9 v; v ref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6v; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test [1] min typ max unit thd 20 log 2nd () 2 3rd () 2 4th () 2 5th () 2 6th () 2 ++++ f 2 ------------------------------------------------------------------------------------------------------------------------------- ------ - =
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 12 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. [1] twos complement reference is inverted msb. [1] x = dont care. table 7: output coding with differential inputs (typical values to agnd); v i(p-p) - v i(p-p) = 1.9 v, v ref =v cca3 - 1.75 v code v i(p-p) v i(p-p) ir binary outputs twos complement outputs [1] d11 to d0 d11 to d0 under?ow <3.125 >4.075 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3.125 4.075 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 -- 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 -- 2047 3.6 3.6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- 4094 -- 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 4095 4.075 3.125 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 over?ow >4.075 <3.125 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 table 8: mode selection otc ce d0 to d11 and ir 0 0 binary; active 1 0 twos complement; active x [1] 1 high-impedance table 9: sample-and-hold selection sh sample-and-hold 1 active 0 inactive; tracking mode fig 3. timing diagram. ds t sample n + 1 sample n clk mbg855 sample n + 2 v l data d0 to d11 t d t h t clkl t clkh high low 50 % high low 50 % data n + 1 data n data n - 1 data n - 2
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 13 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. f ce = 100 khz. fig 4. timing diagram and test conditions of 3-state output delay time. mbg856 50 % 50 % high low t dzh t dhz 50 % high low t dzl t dlz 10 % 90 % output data 0 v v ccd output data 3.3 k w 15 pf s1 v cco tda8768a ce ce test dlz t dzl t dhz t dzh s1 cco v cco v ognd ognd t (1) 40 msps (2) 55 msps (3) 70 msps (1) 40 msps (2) 55 msps (3) 70 msps fig 5. effective number of bits (enob) as a function of input frequency (sample device). fig 6. total harmonic distortion (thd) as a function of input frequency (sample device). 005aaa011 10.4 10.2 9.8 9.4 9 9.6 9.2 10 enob (bits) 10 100 1 f i (mhz) (1) (2) (3) 005aaa012 - 58 - 60 - 64 - 68 - 72 - 66 - 70 - 62 10 100 1 (1) (2) (3) f i (mhz) thd (dbfs)
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 14 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. (1) 40 msps (2) 55 msps (3) 70 msps (1) 40 msps (2) 55 msps (3) 70 msps fig 7. spurious free dynamic range (sfdr) as a function of input frequency (sample device). fig 8. signal-to-noise ratio (snr) as a function of input frequency (sample device). 74 72 68 64 60 66 62 70 sfdr (dbfs) 10 100 1 f i (mhz) (1) (2) 005aaa013 (3) 62 62.5 63 63.5 64 64.5 65 65.5 005aaa014 snr (dbfs) 10 100 1 f i (mhz) (1) (2) (3) fig 9. single-tone; f i = 20 mhz; f clk = 55 msps. -160 -140 -120 -100 -80 -60 -40 -20 0 005aaa015 0 10 17.5 27.5 2.5 5 7.5 12.5 20 25 22.5 15 measured output range (mhz) power spectrum (db)
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 15 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 10. two-tone; f i1 = 20 mhz; f i2 = 20.1 mhz; f clk = 55 msps. -160 -140 -120 -100 -80 -60 -40 -20 0 0 10 17.5 27.5 2.5 5 7.5 12.5 20 25 22.5 15 measured output range (mhz) 005aaa016 power spectrum (db) fig 11. integral non-linearity (inl). -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 005aaa017 0 2048 3584 512 1024 1536 2560 4096 3072 output code output range (inl)
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 16 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 12. differential non-linearity (dnl). 005aaa018 0 2048 3584 512 1024 1536 2560 4096 3072 output code dnl (lsb) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 (1) f i = 4.43 mhz (2) f i = 20 mhz (3) sfdr = 80 db fig 13. sfdr as a function of input amplitude; fs = 1.9 v; f clk = 40 mhz. 20 30 40 50 60 70 80 -60 -50 -40 -30 -20 -10 0 005aaa019 v i (dbfs) sfdr (dbfs) (1) (2) (3)
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 17 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. (1) f i = 4.43 mhz (2) f i = 20 mhz (3) sfdr = 80 db fig 14. spurious free dynamic range (sfdr) as a function of input amplitude; fsref = 1.9 v; f clk = 55 mhz. 20 30 40 50 60 70 80 -60 -50 -40 -30 -20 -10 0 005aaa020 v i (dbfs) sfdr (dbfs) (1) (2) (3) (1) = snr (2) = enob (3) = sfdr fig 15. enob, sfdr and snr as a function of v ref ; f clk = 55 mhz; f i = 4.43 mhz. fig 16. adc full-scale; v i(p-p) - v i(p-p) as a function of v cca - v ref . 60 62 64 66 68 70 72 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 8 8.5 9 9.5 10 10.5 11 005aaa021 (1) (2) (3) v ref (v) (db) bits 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 v cca - v ref (v) (v i - v i ) (p-p) (v) 005aaa022
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 18 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11. application information 11.1 application diagrams the analog, digital and output supplies should be separated and decoupled. fig 17. application diagram. fce003 1 2 3 4 5 6 7 8 9 10 11 12 n.c. n.c. n.c. 13 14 15 16 17 18 19 20 21 22 ir d11 (msb) d10 tda8768a 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 26 25 24 23 27 d2 d1 d0 (lsb) 5 v d3 d4 d5 d6 d7 d8 d9 100 nf 5 v 100 nf 100 nf output format select chip select input 5 v n.c. n.c. n.c. n.c. n.c. clk 100 nf 100 nf 5 v 5 v sh mode v i v i 10 nf 220 nf 100 w 100 w 1:1 v ref 100 nf fig 18. application diagram for differential clock input pecl compatible using a ttl to pecl translator. d pecl 270 w 270 w ttl input fce168 clk clk tda8768a mc100 elt20
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 19 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 19. application diagram for ttl single-ended clock. clk clk ttl input tda8768a fce169
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 20 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11.2 demonstration board c8 = close to tr1 pin. fig 20. demonstration board schematic. fce733 1 cmadc v cco 34 1 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 fl2 s3 s4 v cc v cco v cc v cca 13 12 23 v cca1 2 v cca3 3 agdn3 4 dec 5 n.c. 6 n.c. 7 n.c. 8 9 11 n.c. n.c. 10 v ref do d1 d2 d3 d4 d5 d6 d7 d8 d9 33 ognd clk clk v ccd1 dgnd1 sh agnd4 v cca4 v i v i agnd1 c15 10 nf c6 330 nf c13 100 nf c16 10 nf c10 100 nf c11 100 nf r6 2.4 k w p2 r7 1 k w p1 5 k w 1.2 k w s2 c18 10 nf c5 330 nf r9 100 w r3 50 w c17 10 nf c9 220 nf c8 330 nf d10 d11 ir ce otc dgnd2 n.c v ccd2 n.c n.c fs ref 32 31 30 29 28 27 26 25 24 ic2 tda8768a s1 s5 clk tr1 j1 j3 cmadc clk1 in mclt1_6t_kk81 fl4 v cc r1 100 w c7 330 nf fl3 3 2 4 6 8 10 12 14 16 5 7 9 1113 1517192123 18 20 22 24 c4 1 m f c3 1 m f d2 r5 4.7 k w r2 82 w 3 1 j4 1 j4 2 gnd byd17g d3 ic1 mc78mo5cdt out in 12 v c2 4.7 m f (16 v) bzv55c3v6 v cco v cco tp2 v cc tm3 t1 pmbt 2222a v cc c1 22 m f (20 v) gnd lgt679 d1 750 w r8 v cca r4 50 b11 j2 clk2 10 nf c19 v cca b7 b5 v cca v ccd c14 100 nf c12 100 nf fl1
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 21 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 21. component placement (top side). msd808 f68a21 j4 c4 c5 d2 tp2 p2 c3 d3 r2 r5 r7 r4 r6 c11 c10 c14 p1 r1 r3 j3 j2 j1 1 1 1 1 1 1 12 23 34 c12 s2 s5 s1 s3 s4 b7 b4 b5 b8 b11 c7 c9 r9 fl4 fl2 t1 tm3 tm2 tm1 c2 c1 ic1 ic2 tr1 r8 d1 12 fig 22. component placement (underside). msd809 f68a22 c6 fl1 fl3 c8 c13 c17 c15 c19 c16 c18
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 22 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 23. pcb layout (top layer). fce725 fig 24. pcb layout (ground layer). fce726
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 23 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12. support information 12.1 de?nitions 12.1.1 non-linearities integral non-linearity (inl).: it is de?ned as the deviation of the transfer function from a best ?t straight line (linear regression computation). the inl of the code i is obtained from the equation: where and s = slope of the ideal straight line = code width; i = code value. differential non-linearity (dnl).: it is the deviation in code width from the value of 1lsb. where fig 25. pcb layout (power plane). fce727 inl i () v in i () v in ideal () C s ----------------------------------------------- = i02 n 1 C () = dnl i () v in i1 + () v in i () C s --------------------------------------------- 1 C = i02 n 2 C () =
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 24 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.1.2 dynamic parameters (single tone) figure 26 shows the spectrum of a full-scale input sine wave with frequency f t , conforming to coherent sampling (f t/ f s = m/n, where m is the number of cycles and n is number of samples, m and n being relatively prime), and digitized by the adc under test. remark: in the following equations, p noise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and quantization noise. signal-to-noise and distortion (sinad): the ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the dc component: effective number of bits (enob): it is derived from sinad and gives the theoretical resolution an ideal adc would require to obtain the same sinad measured on the real adc. a good approximation gives: total harmonic distortion (thd): the ratio of the power of the harmonics to the power of the fundamental. for k-1 harmonics the thd is: where the value of k is usually 6 (i.e. calculation of thd is done on the ?rst 5 harmonics). fig 26. spectrum of full-scale input sine wave with frequency f t . magnitude fs/2 sfdr a 1 a 2 a 3 a k s fce710 measured output range sinad db [] 10 p signal p noise distortion + ------------------------------------------ log = enob sinad db [] 176 () C () 602 () = thd db [] 10 p harmonics p signal -------------------------- - log = p harmonics a 2 2 a 3 2 a k 2 ++ = p signal a 1 2 =
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 25 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. signal-to-noise ratio (snr): the ratio of the output signal power to the noise power, excluding the harmonics and the dc component. spurious free dynamic range (sfdr): the number sfdr speci?es available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic, excluding dc component. 12.1.3 intermodulation distortion spectral analysis (dual-tone) from a dual-tone input sinusoid (f t1 and f t2 , these frequencies being chosen according to the coherence criterion), the intermodulation distortion products imd2 and imd3 (respectively, 2nd and 3rd-order components) are de?ned, as follows. imd2 (imd3): the ratio of the rms value of either tone to the rms value of the worst second (third) order intermodulation product. snr db [] 10 p signal p noise ----------------- log = sfdr db [] 20 a 1 max s () ----------------- - log = fig 27. spectral analysis (dual-tone) -160 -140 -120 -100 -80 -60 -40 -20 0 0 10 17.5 27.5 2.5 5 7.5 12.5 20 25 22.5 15 measured output range (mhz) (db) 005aaa023 imd3
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 26 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. the total intermodulation distortion imd is given by where, and is the power in the intermodulation component at frequency f t . 12.1.4 noise power ratio (npr) when using a notch-?ltered broadband white-noise generator as the input to the adc under test, the noise power ratio is de?ned as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the fft spectrum of the adc output sample set. imd db [] 10 p intermod p signal ----------------------- log = p intermod a im 2 f t1 f t2 C () a im 2 f t1 f t2 + () a im 2 f t1 2f t2 C () a im 2 f t1 2f t2 + () a im 2 2f t1 f t2 C () a im 2 2f t1 f t2 + () + + + + C = p signal a 2 f t1 () a 2 f t2 () + = a im 2 f t ()
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 27 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 13. package outline fig 28. sot307-2. unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 28 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 14. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 15. soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 15.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c small/thin packages. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board.
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 29 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 15.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [4] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [5] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [6] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 10: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [3] suitable plcc [4] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [4][5] suitable ssop, tssop, vso not recommended [6] suitable
philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) product data rev. 02 03 july 2002 30 of 32 9397 750 09656 ? koninklijke philips electronics n.v. 2002. all rights reserved. 16. revision history table 11: revision history rev date cpcn description 02 20020703 - product data (9397 750 09656); supersedes preliminary speci?cation tda8768a_1 of 20020409 (9397 750 08323) modi?cations: ? raise to product ? features list corrected ? change value of inl in table 6. 01 20020409 - preliminary data; initial version.
9397 750 09656 philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 02 03 july 2002 31 of 32 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
? koninklijke philips electronics n.v. 2002. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 03 july 2002 document order number: 9397 750 09656 contents philips semiconductors tda8768a 12-bit, 70 msps analog-to-digital converter (adc) 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics. . . . . . . . . . . . . . . . . . . 6 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 application information. . . . . . . . . . . . . . . . . . 18 11.1 application diagrams . . . . . . . . . . . . . . . . . . . 18 11.2 demonstration board . . . . . . . . . . . . . . . . . . . 20 12 support information . . . . . . . . . . . . . . . . . . . . 23 12.1 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12.1.1 non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 23 12.1.2 dynamic parameters (single tone) . . . . . . . . . 24 12.1.3 intermodulation distortion . . . . . . . . . . . . . . . . 25 12.1.4 noise power ratio (npr) . . . . . . . . . . . . . . . . 26 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 14 handling information. . . . . . . . . . . . . . . . . . . . 28 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 15.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 29 15.5 package related soldering information . . . . . . 29 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 31 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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